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data sheet rev.1.0 23.06.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 1 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 em ail: info@swissbit.com of 14 1gb ddr2 C sdram so-dimm 200 pin so-dimm sen01g64e1ch2mt-30 1024mb pc2-5300 in fbga technique rohs compliant environmental requirements: operating temperature (ambient) standard grade 0c to 70c operating humidity 10% to 90% relative humidity, noncondensing operating pressure 105 to 69 kpa (up to 10000 ft.) storage temperature -55c to 100c storage humidity 5% to 95% relative humidity, noncondensing storage pressure 1682 psi (up to 5000 ft.) at 50c options: frequency / latency marking ddr2 667 mhz cl5 -30 module densities 1024mb with 8 dies and 2 ranks standard grade (t a ) 0c to 70c (t c ) 0c to 85c features: 200-pin 64-bit small outline, dual-in-line double data rate synchronous dram module module organization: dual rank 128m x 64 serial presence detect with eeprom dll to align dq and dqs transitions with ck adjustable data-output drive strength gold-contact pad this module family is fully pin and functional compatible to the jedec pc2-5300 spec. and jedec- standard mo 224c. (see www.jedec.org ) the pcb and all components are manufactured according to the rohs compliance specification [eu directive 2002/95/ec restriction of hazardous substances (rohs)] ddr2 - sdram component base micron mt47h64m16 die rev. h 64mx16 ddr2 sdram in fbga-84 package v dd = 1.8v 0.1v, v ddq 1.8v 0.1v auto refresh (cbr) and self refresh 8k refresh every 64ms 1.8v i/o ( sstl_18 compatible) multiple internal device banks for concurrent operation programmable cas latency (cl) posted cas additive latency (al) write latency = read latency C 1 t ck programmable burst length: 4 or 8 four bit prefetch architecture on-die termination (odt) figure: mechanical dimensions
data sheet rev.1.0 23.06.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 2 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 em ail: info@swissbit.com of 14 this swissbit module is an industry standard 200-pin 8-byte ddr2 sdram small outline dual-in-line memor y module (so-dimm) which is organized as x64 high spe ed cmos memory arrays. the module uses internally configured oct-bank ddr2 sdram devices. the module u ses double data rate architecture to achieve high- speed operation. ddr2 sdram modules operate from a differential clock (ck and ck#). read and write accesses to a ddr2 sdram module is burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequ ence. the burst length is either four or eight locat ions. an auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst access. the ddr2 sdram devices have a multibank arch itecture which allows a concurrent operation that i s providing a high effective bandwidth. a self refres h mode is provided and a power-saving power-down mode. all inputs and all full drive-strength outputs are sstl_ 18 compatible. the ddr2 sdram module uses the optional serial prese nce detect (spd) function implemented via serial eeprom using the standard i 2 c protocol. this nonvolatile storage device contains 256 bytes. the first 128 bytes are utilized by the so-dimm manufacturer (swissbit) to identify the module type, the modules organiza tion and several timing parameters. the second 128 bytes are available to the end user. module configuration organization ddr2 sdrams used row addr. device bank select col. addr. refresh module bank select 128m x 64bit 8 x 64m x 16bit (1gbit) 13 ba0, ba1, ba2 10 8k s0#, s1# module dimensions in mm 67.60 (long) x 25.4(high) x 3.80 [max] (thickness) timing parameters part number module density transfer rate memory clock/data bit rate latency SEN01G64E1CH2MT-30R 1024 mb 5.3 gb/s 3.0ns/667mt/s 5 300-555 pin name a0-9, a11 C a12 address inputs a10/ap address input / autoprecharge bit ba0 Cba2 bank address inputs dq0 C dq63 data input / output dm0-dm7 input data mask ras# row address strobe cas# column address strobe we# write enable cke0 C cke1 clock enable
data sheet rev.1.0 23.06.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 3 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 em ail: info@swissbit.com of 14 ck0 C ck1 clock inputs, positive line ck0# C ck1# clock inputs, negative line dqs0 - dqs7 data strobe, positive line dqs0# - dqs7# data strobe, negative line (only used when differential data strobe mode is enabled) s0#, s1# chip select v dd supply voltage (1.8v 0.1v) v ref input / output reference v ss ground v ddspd serial eeprom positive power supply scl serial clock for presence detect sda serial data out for presence detect sa0 C sa1 presence detect address inputs odt0, odt1 on-die termination nc no connection pin configuration pin # front side pin # back side pin # front side pin # back side 1 v ref 2 v ss 101 a1 102 a0 3 v ss 4 dq4 103 v dd 104 v dd 5 dq0 6 dq5 105 a10/ap 106 ba1 7 dq1 8 v ss 107 ba0 108 ras# 9 v ss 10 dm0 109 we# 110 s0# 11 dqs0# 12 v ss 111 v dd 112 v dd 13 dqs0 14 dq6 113 cas# 114 odt0 15 v ss 16 dq7 115 s1# 116 nc/a13 17 dq2 18 v ss 117 v dd 118 v dd 19 dq3 20 dq12 119 odt1 120 nc 21 v ss 22 dq13 121 v ss 122 v ss 23 dq8 24 v ss 123 dq32 124 dq36 25 dq9 26 dm1 125 dq33 126 dq37 27 v ss 28 v ss 127 v ss 128 v ss 29 dqs1# 30 ck0 129 dqs4# 130 dm4 31 dqs1 32 ck0# 131 dqs4 132 v ss 33 v ss 34 v ss 133 v ss 134 dq38 35 dq10 36 dq14 135 dq34 136 dq39 37 dq11 38 dq15 137 dq35 138 v ss 39 v ss 40 v ss 139 v ss 140 dq44 41 v ss 42 v ss 141 dq40 142 dq45 43 dq16 44 dq20 143 dq41 144 v ss 45 dq17 46 dq21 145 v ss 146 dqs5# 47 v ss 48 v ss 147 dm5 148 dqs5 49 dqs2# 50 nc 149 v ss 150 v ss 51 dqs2 52 dm2 151 dq42 152 dq46
data sheet rev.1.0 23.06.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 4 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 em ail: info@swissbit.com of 14 pin # front side pin # back side pin # front side pin # back side 53 v ss 54 v ss 153 dq43 154 dq47 55 dq18 56 dq22 155 v ss 156 v ss 57 dq19 58 dq23 157 dq48 158 dq52 59 v ss 60 v ss 159 dq49 160 dq53 61 dq24 62 dq28 161 v ss 162 v ss 63 dq25 64 dq29 163 nc 164 ck1 65 v ss 66 v ss 165 v ss 166 ck1# 67 dm3 68 dqs3# 167 dqs6# 168 v ss 69 nc 70 dqs3 169 dqs6 170 dm6 71 v ss 72 v ss 171 v ss 172 v ss 73 dq26 74 dq30 173 dq50 174 dq54 75 dq27 76 dq31 175 dq51 176 dq55 77 v ss 78 v ss 177 v ss 178 v ss 79 cke0 80 cke1 179 dq56 180 dq60 81 v dd 82 v dd 181 dq57 182 dq61 83 nc 84 nc 183 v ss 184 v ss 85 nc/ba2 86 nc 185 dm7 186 dqs7# 87 v dd 88 v dd 187 v ss 188 dqs7 89 a12 90 a11 189 dq58 190 v ss 91 a9 92 a7 191 dq59 192 dq62 93 a8 94 a6 193 v ss 194 dq63 95 v dd 96 v dd 195 sda 196 v ss 97 a5 98 a4 197 scl 198 sa0 99 a3 100 a2 199 v ddspd 200 sa1
data sheet rev.1.0 23.06.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 5 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 em ail: info@swissbit.com of 14 functional block diagramm 1024mb ddr2 sdram sodimm, 2 ranks and 8 components
data sheet rev.1.0 23.06.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 6 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 em ail: info@swissbit.com of 14 maximum electrical dc characteristics parameter/ condition symbol min max units supply voltage v dd -1.0 2.3 v i/o supply voltage v dd q -0.5 2.3 v v dd l supply voltage v dd l -0.5 2.3 v voltage on any pin relative to v ss v in , v out -0.5 2.3 v input leakage current any input 0v v in v dd, v ref pin 0v v in 0.95v (all other pins not under test = 0v) command/address ras#, cas#, we#, s#, cke -40 40 ck, ck# -20 20 dm i i -5 5 a output leakage current (dqs and odt are disabled; 0v v out v dd q) dq, dqs, dqs# i oz -5 5 a v ref leakage current ; v ref is on a valid level i vref -16 16 a dc operating conditions parameter/ condition symbol min nom max units supply voltage v dd 1.7 1.8 1.9 v i/o supply voltage v dd q 1.7 1.8 1.9 v v dd l supply voltage v dd l 1.7 1.8 1.9 v i/o reference voltage v ref 0.49 x v dd q 0.50 x v dd q 0.51x v dd q v i/o termination voltage (system) v tt v ref C 0.04 v ref v ref + 0.04 v input high (logic 1) voltage v ih (dc) v ref + 0.125 v dd q + 0.3 v input low (logic 0) voltage v il (dc) -0.3 v ref C 0.125 v ac input operating conditions parameter/ condition symbol min max units input high (logic 1) voltage v ih (ac) v ref + 0.25 - v input low (logic 0) voltage v il (ac) - v ref - 0.25 v capacitance at ddr2 data rates, it is recommended to simulate t he performance of the module to achieve optimum val ues. when inductance and delay parameters associated wit h trace lengths are used in simulations, they are significantly more accurate and realistic than a gr oss estimation of module capacitance. simulations c an then render a considerably more accurate result. jedec m odules are now designed by using simulations to clo se timing budgets.
data sheet rev.1.0 23.06.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 7 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 em ail: info@swissbit.com of 14 i dd specifications and conditions (0c t case + 85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) max. parameter & test condition symbol 5300-555 unit operating current *) : one device bank active-precharge; t rc = t rc (i dd ); t ck = t ck (i dd ); cke is high, cs# is high between valid commands; dq inputs changing once per clock cycle; address an d control inputs changing once every two clock cycles i ddo 568 ma operating current :*) one device bank; active-read-precharge; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address inputs changing once every two clock cycles; data pattern is same as i dd4w i dd1 548 ma precharge power-down current: all device banks idle; power-down mode; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref i dd2p 56 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all control and address bus inputs are not changing ; dqs are floating at v ref i dd2q 520 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all other control and address bus inputs are changi ng once every two clock cycles; dq inputs changing onc e per clock cycle i dd2n 560 ma fast pdn exit mr[12] = 0 240 active power-down current: all device banks open; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref slow pdn exit mr[12] = 1 i dd3p 80 ma active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; all other control and address bus inputs are changi ng once every two clock cycles; dq inputs changing onc e per clock cycle i dd3n 600 ma operating read current: all device banks open, continuous burst reads; one module rank active; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4r 908 ma
data sheet rev.1.0 23.06.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 8 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 em ail: info@swissbit.com of 14 max. parameter & test condition symbol 5300-555 unit operating write current: all device banks open, continuous burst writes; one module rank active; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are changing once every two cloc k cycles; dq inputs changing once per clock cycle i dd4w 828 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval, cke is high, cs# is high between valid commands; all other control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd5 2160 ma self refresh current: ck and ck# at 0v; cke 0.2v; all other control and address bus inputs are floating at v ref ; dqs are floating at v ref i dd6 56 ma operating current*) : four device bank interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) C 1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address bus inputs are not changing during deselect; dq inputs changing once per clock cycle i dd7 1428 ma *) value calculated as one module rank in this oper ating condition, and all other module ranks in idd2p (cke low) mode. timing values used for i dd measurement i dd measurement conditions symbol 5300-555 unit cl (i dd ) 5 t ck t rcd (i dd ) 15 ns t rc (i dd ) 60 ns t rrd (i dd ) 7.5 ns t ck (i dd ) 3.0 ns t ras min (i dd ) 45 ns t ras max (i dd ) 70,000 ns t rp (i dd ) 15 ns t rfc (i dd ) 105 ns
data sheet rev.1.0 23.06.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 9 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 em ail: info@swissbit.com of 14 ddr2 sdram component electrical characteristics and reco mmended ac operating conditions (0c t case + 85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) ac characteristics 5300-555 parameter symbol min max unit clock cycle time cl = 5 t ck (5) 3.0 8.0 ns cl = 4 t ck (4) 3.75 8.0 ns cl = 3 t ck (3) 5.0 8.0 ns ck high-level width t ch 0.45 0.55 t ck ck low-level width t cl 0.45 0.55 t ck half clock period t hp min (t ch, t cl ) ps access window (output) of dq s from ck/ck# t ac -0.45 +0.45 ns data-out high-impedance window from ck/ck# t hz +0.45 (= t ac max) ns data-out low-impedance window from ck/ck# t lz -0.45 (= t ac min) +0.45 (= t ac max) ns dq and dm input setup time relative to dqs t dsa 0.10 ns dq and dm input hold time relative to dqs t dha 0.30 ns dq and dm input setup time relative to dqs t dsb 0.10 ns dq and dm input hold time relative to dqs t dhb 0.175 ns dq and dm input pulse width ( for each input ) t dipw 0.35 t ck data hold skew factor t qhs 0.34 ns dq-dqs hold, dqs to first dq to go non-valid, per access t qh t hp - t qhs ns data valid output window t dvw t qh - t dqsq ns dqs input high pulse width t dqsh 0.35 t ck dqs input low pulse width t dqsl 0.35 t ck dqs output access time from ck/ck# t dqsck -0.40 +0.40 ns dqs falling edge to ck rising - setup time t dss 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 t ck dqs Cdq skew, dqs to last dq valid, per group, per access t dqsq 0.24 ns dqs read preamble t rpre 0.9 1.1 t ck dqs read postamble t rpst 0.4 0.6 t ck dqs write preamble t wpre 0.35 t ck dqs write preamble setup time t wpres 0 ns dqs write postamble t wpst 0.4 0.6 t ck positive dqs latching edge to associated clock edge t dqss - 0.25 + 0.25 t ck write command to first dqs latching transition wl- t dqss wl+ t dqss t ck address and control input pulse width ( for each input ) t ipw 0.6 t ck address and control input setup time t isa 0.4 ns
data sheet rev.1.0 23.06.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 10 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 em ail: info@swissbit.com of 14 ddr2 sdram component electrical characteristics and reco mmended ac operating conditions (continued) (0c t case + 85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) ac characteristics 5300-555 parameter symbol min max unit address and control input hold time t iha 0.4 ns address and control input setup time t isb 0.20 ns address and control input hold time t ihb 0.275 ns cas# to cas# command delay t ccd 2 t ck active to active (same bank) command period t rc 55 ns active bank a to active bank b command t rrd 7.5 ns active to read or write delay t rcd 15 ns four bank activate period t faw 37.5 ns active to precharge command t ras 40 70,000 ns internal read to precharge command delay t rtp 7.5 ns write recovery time t wr 15 ns auto precharge write recovery + precharge time t dal t wr + t rp ns internal write to read command delay t wtr 7.5 ns precharge command period t rp 15 ns precharge all command period t rpa t rp + t ck ns load mode command cycle time t mrd 2 t ck cke low to ck, ck# uncertainty t delay t is + t ck + t ih t ck refresh to active or refresh to refresh command interval t rfc 105 70,000 ns average periodic refresh interval (0c<= t case <= 85 c) t refi 7.8 s (85c<= t case <= 95 c) t refi 3.9 s exit self refresh to non- read command t xsnr t rfc (min) + 10 ns exit self refresh to read command t xsrd 200 t ck exit self refresh timing reference t isxr t is ps odt turn-on delay t aond 2 2 t ck odt turn-on t aon t ac (min) t ac (max) + 1,000 ps odt turn-off delay t aofd 2.5 2.5 t ck odt turn-off t aof t ac (min) t ac (max) + 600 ps odt turn-on (power-down mode) t aonpd t ac (min) + 2,000 2 x t ck + t ac (max) + 1,000 ps odt turn-off (power-down mode) t aofpd t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 ps odt to power-down entry latency t anpd 3 t ck
data sheet rev.1.0 23.06.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 11 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 em ail: info@swissbit.com of 14 ddr2 sdram component electrical characteristics and reco mmended ac operating conditions (continued) (0c t case + 85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) ac characteristics 5300-555 parameter symbol min max unit odt power-down exit latency t axpd 8 t ck odt enable from mrs command t mod 12 ns exit active power-down to read command, mr [bit 12 = 0] t xard 2 t ck exit active power-down to read command, mr [bit 12 = 1] t xards 7 C al t ck exit precharge power-down to any non-read command t xp 2 t ck cke minimum high/low time t cke 3 t ck
data sheet rev.1.0 23.06.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 12 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 em ail: info@swissbit.com of 14 serial presence-detect matrix byte description 5300-555 0 number of spd bytes used 0x80 1 total number of bytes in spd device 0x08 2 fundamental memory type 0x08 3 number of row addresses on assembly 0x0d 4 number of column addresses on assembly 0x0a 5 dimm hight and module ranks 0x21 6 module data width 0x40 7 module data width (continued) 0x00 8 module voltage interface levels (v dd q) 0x05 9 sdram cycle time, (t ck ) [max cl] cas latency = 5 (5300), cl = 4 (4200) 0x30 10 sdram access from clock, (t ac ) [max cl] cas latency = 5 (5300); cl = 4 (4200) 0x45 11 module configuration type 0x00 12 refresh rate / type 0x82 13 sdram device width (primary sdram) 0x10 14 error- checking sdram data width 0x00 15 minimum clock delay, back-to-back random column access 0x00 16 burst lengths supported 0x0c 17 number of banks on sdram device 0x08 18 cas latencies supported 0x38 19 module thickness 0x01 20 ddr2 dimm type 0x04 21 sdram module attributes 0x00 22 sdram device attributes: weak driver and 50 w odt 0x03 23 sdram cycle time, (t ck ) [max cl C 1] cas latency = 4 (5300), cl = 3 (4200) 0x3d 24 sdram access from ck, (t ac ) [max cl C 1] cas latency = 4 (5300), cl = 3 (4200) 0x45 25 sdram cycle time, (t ck ) [max cl C 2] cas latency = 3 (5300) 0x50 26 sdram access from ck, (t ac ) [max cl C 2] cas latency = 3 (5300) 0x45 27 minimum row precharge time, (t rp ) 0x3c 28 minimum row active to row active, (t rrd ) 0x28 29 minimum ras# to cas# delay, (t rcd ) 0x3c 30 minimum ras# pulse width, (t ras ) 0x2d 31 module bank density 0x80
data sheet rev.1.0 23.06.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 13 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 em ail: info@swissbit.com of 14 serial presence-dtect matrix (continued) byte description 5300-555 32 address and command setup time, (t isb ) 0x20 33 address and command hold time, (t ihb ) 0x27 34 data / data mask input setup time, (t dsb ) 0x10 35 data / data mask input hold time, (t dhb ) 0x17 36 write recovery time, (t wr ) 0x3c 37 write to read command delay, (t wtr ) 0x1e 38 read to precharge command delay, (t rtp ) 0x1e 39 mem analysis probe 0x00 40 extension for bytes 41 and 42 0x06 41 min active auto refresh time, (t rc ) 0x3c 42 minimum auto refresh to active / auto refresh command period, (t rfc) 0x7f 43 sdram device max cycle time, (t ckmax ) 0x80 44 sdram device max dqs-dq skew time, (t dqsq ) 0x18 45 sdram device max read data hold skew factor, (t qhs ) 0x22 46 pll relock time 0x00 47-61 optional features, not supported 0x00 62 spd revision 0x13 63 checksum for bytes 0-62 0x40 64-67 manufacturer`s jedec id code 0x7f7f7fda 68-71 manufacturer`s jedec id code (continued) 0x00 72 manufacturing location x 73-90 module part number (ascii) sen01g64e1ch2mt- 30r 91 pcb identification code 0x52 92 identification code (continued) 0x00 93 year of manufacture in bcd x 94 week of manufacture in bcd x 95-98 module serial number x 99-127 manufacturer-specific data (rsvd) 0x00 128- 255 open for customer use 0xff part number code s e n 01g 64 e1 c h 2 mt - 30 * r 1 2 3 4 5 6 7 8 9 10 11 12 13 *rohs compl. swissbit ag ddr2-667mhz sdram d dr 2 200 pin unbuffered 1.8v chip vendor (micron) depth (1024mb) 2 module ranks width chip rev. h pcb-type (b62srcg-250) chip organisation x16 * optional / additional information
data sheet rev.1.0 23.06.2010 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 14 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 em ail: info@swissbit.com of 14 locations swissbit ag industriestrasse 4 C 8 ch C 9552 bronschhofen switzerland phone: +41 (0)71 913 03 03 fax: +41 (0)71 913 03 15 _____________________________ swissbit germany gmbh wolfener strasse 36 d C 12681 berlin germany phone: +49 (0)30 93 69 54 C 0 fax: +49 (0)30 93 69 54 C 55 _____________________________ swissbit na, inc. 14 willett avenue, suite 301a port chester, ny 10573 usa phone: +1 914 935 1400 fax: +1 914 935 9865 _____________________________ swissbit na, inc. 3913 todd lane, suite C 307 austin, tx 78744 usa phone: +1 512 302 9001 fax: +1 512 302 4808 _____________________________ swissbit japan, inc. 3f core koenji, 2-1-24 koenji-kita, suginami-ku, tokyo 166-0002 japan phone: +81 3 5356 3511 fax: +81 3 5356 3512

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